Software generation of Three Phase Sinusoidal PWM

In a sinusoidal PWM, signals are modulated sinusoidally, as shown in figure below. Note how duty-cycles of PWM changes in proportion to amplitudes of a reference sine wave. 

A single phase sinusoidal PWM (ref)

For three phase sinusoidal PWM (SPWM) waves, simply generate PWMs using three such modulating sine waves 120° from each other, as shown below:

                                     A three-phase Sinusoidal PWM (ref)

How to generate PWMs - 

(A) Analog approach

The SPWM (three phase or a single) can be generated by continually comparing a reference sine wave (three phase or a single) with a triangular wave using an opamp comparator.

(B) Digital approach - 

Digitally (using FPGAs, microcontrollers or dedicated ICs), one approach would be to calculate signals.

However, a much preferred (and a usual) approach  makes use of predefined look-up tables of signal pulse widths.

Lets use an 8-bit for our look up tables. 

First, let us quantize the amplitude of the sinusoidal wave in 8 bits. The negative peak of the sine wave will be zero and the positive peak as 255 as given by the following equation.

PWM_duty-cycle= 127*sin f+128, 0 £ f £ 2p .      

Above equation is for a single phase. For three phase, equations will be:

Phase R PWM_duty-cycle=127*sin f+128

Phase Y PWM_duty-cycle=127*sin (f+120°) +128

Phase B PWM_duty-cycle=127*sin (f+240°) +128

However, "f" has to be digitized too. Using 8-bits, f_8-bit= (k/256) x 2p, where 0 £ k £ 255.

This will result in: (for a single phase)

PWM_duty-cycle= 127*sin {(k/256) x 2p} + 128, 0 £ k £ 255                

Above final equation will give us a 8-bit value for PWMs that we can store in a look-up table 256 long (each storing a byte). Note, the equation will result in floating numbers which needs to rounded up or down as appropriate.

A Verilog snippet code below shows the data in the look-up table: (best viewed in Chrome browser)

//note 256 locations each storing 8-bit long data (PWM)   //each location represents an angle location/time  case(addr)                                            //angle:   data=PWM;                               8'd00:      data=8'd128;                           8'd01:      data=8'd131;                           8'd02:      data=8'd134;                           ....                                                      8'd254:      data=8'd122;                          8'd255:      data=8'd125;                        endcase

(We can create similar table using C/C++ or any other language).

The table is for a single phase. For three phase, we may be inclined to create three different look-up tables, one for each phase. However, such an approach will require more memory space. Rather what we should do is to read from three locations (each 120° apart).In other words, if a duty-cycle value for the first phase is read at 0° (0th place) for the first phase, values from 120° (85th place) and 240° (171th place) are read for the second and the third phase, respectively from the look-up table.

How to establishing the desired sinusoidal frequency? 

It is Simple. The rate of reading the duty-cycles from the look-up table will give us the desired sinusoidal  frequency - simply read from the table at the desired frequency rate.

Determining parameters for Emitter Couple Logic (MC10102P quad NOR)

ECL is based on current mode logic and transistors don’t need to go into saturation mode which means the propagation delay in this family is best compared to any other family compared. But corresponding logic swing is much less in ECL than for other family. Also, correspondingly power consumption was high which was tradeoff in this logic family. But because of emitter follower output stage at ECL, there is a good fanout in this logic. 

Just like other ICs (previous blogs), lets measure the V_OL and V_OH of the MC10102P quad NOR gate as well as to measure its propagation times by forming a ring oscillator. 

Circuit setup to measure the VTC parameters

This is what I got,

	As Measured	From datasheet
VOH	- 0.89 V	- 0.81 V
VOL	- 1.62 V	- 1.65 V

Next, I went to measure the average propagation delay of the IC using ring oscillator technique:

Circuit setup for the ring oscillator

I got the following result:

which gives me the following result:

foscillation (MHz)	Time period, T=1/ foscillation	Average propagation delay, tp=T/ (2*3)
99.01	10.1 nS	1.68 nS

                           A comparison between the measured data and the datasheet data

	From measurement	From datasheet
tP	1.68 nS	2 nS

Of all ICs tested so far, the ECL shows the least propagation delay.

Determining parameters for SN74LS02 TTL NOR schottky diode

Now, what would I get if I repeated the similar experiments (see previous blogs on standard TTL) with a schottky diode; meaning the V_OL ,V_OH , etc

This is what I got:

	As Measured	From Datasheet
VOH	3.2 V	3.4 V (Test conditions: Vcc=4.75V, IOH= - 0.4 mA)
VOL	0.12 V	0.4V (Test conditions: Vcc=4.75V, IOL= 4 mA)
tPLH	13.86 nS	10 – 15 nS
tPHL	1.52 nS	10 – 15 nS
Frequency	23.36 MHz	----
tP	7.13 nS	10 – 15 nS

Note the Schottky logics will have a better propagation delay as they contain Schottky diode clamp across the base-collector junction of the transistor, causing the transistor never go to saturation. This meant an improved turn-off period. But my measurement showed the Schottky NOR gate had more propagation delay (tpLH) which I would attribute to my experimental setup like length of the wires, breadboard connections etc introducing various parasitic capacitances. (The charging and discharging of these parasitic capacitances could have introduced the noted additional delays).

For the VTC parameters, it was noted that the speficied V_OLmax for the schottky logic was nearly double that for the standard TTL logic. That was because use of the Schottky diode clamped the output at 0.4 V instead of normal saturation value of 0.2 V. It meant the lower value of logic swing for Schottky logic, and subsequently the lower Fanout. 

Determining the average propagation delay of the inverter using ring oscillator

Next I wanted to determine the average propagation delay of the inverter (using NOR SN7402 connected as NOT gates) using ring oscillator, see the schematic below:

I looked at the signal flowing around the feedback (the signal can be measured at any point, and should give the same result).

From the trace, we see the oscillation of 32.89 MHz; Ha! that will give me the propagation delay! Here is how I calculated:

Computation for the propagation delay

foscillation (MHz)	Time period, t=1/ foscillation	Average propagation delay, tp=t/(2*3)
32.89	30.4 nS	5.07 nS

Now, comparing with the datasheet, it showed the value was well within the datasheet (note the datasheet always indicate the "Max" delay; everyone wants lower propagation delay!!!)

Comparison of the propagation delays

	As Measured	From Datasheet
tp	5. 07 nS	10 -18 nS

The better value (than datasheet) is possibly because with three inverters in a positive feedback, the propagation delay so obtained was average of the three. (A gotcha "note"- this is in a positive feedback loop; the propagation delay is simply not the linear sum of three values in each.) Any worse performance on one was compensated by this averaging effect. Also note, as no external input was used, it meant rise and fall time of the input waveform will have no effect upon measurement.

Measuring VTC parameters of a digital IC

To measure the VTC parameters for SN7402, I had the following schematics:

For V_OH:                                                              

          

For V_OL: 

       

How did I come up with the resistances? Here's how - per the datasheet, the required V_OH was 3.4 V and V_OL was 0.2V.

With Required V_OH =3.4 V for I_OH= - 0.4 mA (per datasheet), which gave me pulldown resistor as:

Similarly, the Required V_OL =0.2 V for I_OL= 16 mA (datasheet) and V_CC=4.75 V gave me the pullup resistor as:

But since calculated resistances weren’t available, following values were used-

R_pull-down=8.1 kW

R_pull-up= 268 kW

Here is the result of my folly:

	As Measured	From Datasheet
VOH	3.38 V	3.4 V  (Test conditions: Vcc=4.75V, IOH= - 0.4 mA)
VOL	0.220 V	0.2 V (Test conditions: Vcc=4.75V, IOL= 16 mA)

The measured value is different from the datasheet since I had used different resistors. Note the Logic Swing of the output was 3.16V.

Measuring propagation delay of a logic IC

I wanted to measure the propagation delay through a single SN7402 TTL NOR gate. For this, I used the same conditions as specified by the manufacturer so as to make comparison with regards to the manufacturer’s specifications. The circuit is shown below:

At its input, I connected a function generator as a 5Vpk step function. The signals were measured both at the input and the output. I got the following result:

For ON to OFF transition at the output of the NOR:

                                     

For OFF to ON transition at the output of the NOR:

This would give me the results as:

Propagation delays as measured

td (nS)	tf (nS)	ts (nS)	tr (nS)	tPHL=td +tf/2 (nS)	tPLH=ts +tr/2 (nS)
6	12.4	15	28	12.2	29

I repeated the experiment with the CL removed, I got the following results:

tPLH	3.2 nS
tPHL	10 nS

Note: For the second case, t_PLH and t_PHL were determined by measuring midpoints of transition between input and output waveforms.

Now, comparing with the datasheet, we have:

	As Measured	From Datasheet
	With CL
tPLH	12.2 nS	8 – 15 nS
tPHL	29 nS	12 – 22 nS
	Without CL
tPLH	3.2 nS	8 – 15 nS
tPHL	10 nS	12 – 22 nS

With the use of load capacitance C_L, the measured values for t_PLH and t_PHL were more than the range in the datasheet. Removing the load capacitor improved the result (and also well within the datasheet). I believe the previous measurement was likely affected by the experimental setup, mainly the input capacitance of the oscilloscope. Besides, parasitic capacitances due to other setups like between leads, breadboard connections would have added up with that of the load effecting the total propagation delay.