ASIC Design - a simple example

The final ASIC for our simple example design

Here is a simple example of an ASIC design. Hopefully, this will also provide a good example on how an ASIC design differs from an FPGA design.


Objective
In this design, we shall be developing a BCD to seven segment decoder for a 16-bit word. In the process, you will be familiarized with basic necessary to transform a system level or gate level digital design into an IC layout in preparation for actual fabrication.

Tools used:
- Tanner EDA tool


Background

The figure, above shows a BCD to Seven Segment Decoder which can display (0 to 9) for various combinations of inputs b3 to b0. Based on the truth table for such a logic, we develop a circuit corresponding to the above truth table is shown below. This corresponds to a single BCD word only.

A gate schematic for a single BCD word

  We are developing a 16-bit word circuit. The block diagram below represents the final schematic. 

Schematic Drawing

For the schematic preparation following steps were taken:

i)                S-Edit v12.1 was opened from Tanner EDA software. (see here for tutorial)

ii)              The design name was given. (File->New Design-> Design Name)

iii)            The cell was clicked from main menu. (Cell->Newview).

iv)             “scmos.tanner” was used as the library for standards cells and the schematic was drawn.  

SPICE simulation (to verify):

    After which the schematic was exported in T-SPICE (see here for tutorial) to observe the output.

i)                This file was then exported to T-SPICE (File->Export->Export SPICE). 

ii)              Then a netlist was generated. 

iii)            For the purpose of simulation, the file ml2_20.md was included and then we observed the waveforms in W-Edit. ( ml2_20.md defines the level and pmos, nmos of devices etc)

iv)    A PSPICE code was added in the netlist generated by schematic and timing diagrams generated to verify.

Layout generation for the designed chip

          Once, the circuit was verified, time is for the layout generation. For the layout generation, the Standard Cell Place and Route (SPR) approach available in Tanner tools was used. The full custom layout approach could have been used (given its higher transistor density for proper design) but that would have been too tedious (especially noting 480 transistors in the designed circuit).

        For the Tanner software, SPR approach is taken by first having (or creating) the library of standard cell frames. With these in hand and creating the desired schematic in the S-Edit, the schematic has to be exported as .tpr file (tanner place and route file ) into the L-Edit where an automatic (standard) place and route could be done. The process is summarized by the figure below:

SPR process in Tanner software

Procedures taken -

i)     In S-Edit, the drawn and verified circuit schematic was selected using,        

S-Edit > Edit > Select All

ii)   Then, new property was added to the schematic as TPR.OUTPUT which is not written to the netlist, instead is used to instruct S-Edit in exporting the module as a pad or as a regular cell in a TPR-format.

  View->Properties->Add properties-> Name = TPR.OUTPUT

iii) Since the S-Edit considers the module a pad only with the property value of CP. So, the pads were assigned “CP” as values for TPR.OUTPUT property and the gates “C”.

iv) Then the “.tpr” file was exported using  File->Export->Export TPR

v)  In the L-Edit, new layout file was created using the TDB file, lights.tdb.

File->New->Layout->Copy TDB setup file->...\lights.tdb.

vi)  The feature size was chosen with the Lamba as 1 Lambda = 1.0 Micron.

vii) Then, the layout was generated by

L-Edit >Tools>SPR>Place and Route>Setup> Netlist file> filename.tpr > Initialize setup>Run.

The options within SPR>Place and Route> “Padframe generation” and “Pad route” have to be selected to generate layout with the frame. And these have to be deselected to generate layout without the frame. Note various layouts include areas for PMOS, , NMOS, and so on.

 

The SPR summary file for the case with the frame indicated following interesting points-

Core size in Lambda  :  698.00 x 1187.00

Core area (Lambda^2) :  828526.00

Frame size in Lambda  :  2464.00 x 2644.00

With the lambda being chosen as 1 micron, the chip frame size was 6514816 micron². This was when the placement optimization factor of 1.00 was used. 

 

Pin-out for the designed chip

     The designed chip has 46 Pins with 16 input pins, 28 output pins, and single pins for V_DD and V_Gnd.  The process of determining the pin layout are discussed below:

Procedure used in determining the pins for input/outputs:

A]  Pin Layout for the single BCD to seven segment decoder:

Initially, the Pin Layout for a single BCD to seven segment decoder was determined, the main objective being to gain confidence that the process works (since 4-bit word is easier to work than 16-bit).

Following steps were followed:

1. In S-Edit v12.1, system names for Input and Output pads were found out as:
1. Clicking View > Properties >  System>Name>PadName 
2.  By clicking “Tools>SPR Setup>Padframe Setup…>Layout” :                                                               From this list, the proper input/output signals were mapped onto the pin.

      2 .Then, by carefully verifying across the layouts, the pinouts for the signals were verified and finally pins were labeled as on figure below:

Pin Layout for the Single BCD to seven segment decoder (with frame)

 Note this is not our final circuit, we are looking for a 16-bit. Here we repeat same thing as discussed above. And our final pin layout is:

Our final ASIC - Pin Layout for 16 bit word to seven segment decoder (with frame)

And that completes our example of the ASIC design.

(Had this been an FPGA design, the entire exercise would have been covered by few lines of HDL code).

Note - there were several layouts files that were generated. Had this been a real exercise, those files would be shipped to fab labs for production. 

see FPGA vs ASIC Design