Monday, November 17, 2014

FPGA vs ASIC design


I still remember that day when my VLSI professor started a lecture on ASIC. The very first thing I asked her was how it is different from FPGA. As I have treaded my professional career during these so many years, I get pleasantly amused when I see this question repeated by so many novice but curious young engineers. Certainly, this must be one popular question.

For benefit of all, here is what my professor told me succintly:

An FPGA is a piece of programmable logic.     It is quite flexible allowing rapid implementation of logic onto the silicon. 
An ASIC is a "specially designed" specialized chip to perform specific function (to operate at higher performance levels). ASIC is designed to be maximally optimized in terms of gates and logic.

Here is a table from Xilinx that provides an excellent descriptions of the difference:
FPGA Design
AdvantageBenefit
Faster time-to-marketNo layout, masks or other manufacturing steps are needed
No upfront non-recurring expenses (NRE)Costs typically associated with an ASIC design
Simpler design cycleDue to software that handles much of the routing, placement, and timing
More predictable project cycleDue to elimination of potential re-spins, wafer capacities, etc.
Field reprogramabilityA new bitstream can be uploaded remotely
ASIC Design
AdvantageBenefit
Full custom capabilityFor design since device is manufactured to design specs
Lower unit costsFor very high volume designs
Smaller form factorSince device is manufactured to design specs
 From Xilinx again, the figure below shows how the FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis etc of the ASIC design. No doubt, time-to-market is faster in FPGA.

In comparison, ASIC design involves significant complexity and time (read money). 

Another interesting thing to note is FPGA designers mostly perform their test on an actual FPGA to be deployed whereas ASIC designers will be running tests on simulators in their workstations.

See a simple example on ASIC Design


No comments:

Post a Comment