ISE Configuration and Programming Overview

After generating a programming file using the Generate Programming File process, you can configure your device, create PROM, System ACE™ solution, SVF, XSVF, or STAPL files. You can configure FPGAs or program Xilinx® CPLDs or PROMs in-system, directly from a host-computer using iMPACT with a Xilinx download cable.

Note For detailed information on using iMPACT, see the iMPACT Help. In the Help Viewer, click the Synchronize TOC button to view all related Help topics.

To Configure or Program a Device

To configure or program a device, do the following:

1.  Connect the cable to an appropriate port on the host computer and to the correct pins on the target board.
   When setting up the configuration chain and target device to configure or program a device, select the appropriate configuration mode, which is used to connect to the board from your Xilinx download cable. The most commonly used mode is Boundary Scan. When using this mode, you must connect the cable leads to the following pins: TDO, TDI, TCK, TMS, VCC, and GND. For more information, see the Data Sheets or Device User Guides the for the device you are targeting.
2.  In the Design panel, select Implementation from the Design View drop-down list.
3.  In the Hierarchy pane, select the top module .
4.  Optional. Right-click Configure Target Device, and select Process Properties to set the Configure Target Device Properties.
5.  In the Processes pane, double-click Configure Target Device
   The first time you configure your device, the tools walk you through the process of setting up a configuration chain and designating your target device. On subsequent runs, the tools use the settings stored in your iMPACT Project File (IPF). To edit the IPF file, use the Manage Configuration Project (iMPACT) process.

To Generate Related Configuration Files

Optionally, you can generate configuration files to program a configuration device, such as a PROM or System ACE device, or to use with other software programs as follows:

1.  In the Design panel, select Implementation from the Design View drop-down list.
2.  In the Hierarchy pane, select the top module .
3.  In the Processes pane, expand Configure Target Device, and do one of the following:
   •  To generate PROM/ACE files (FPGAs only), double-click Generate Target PROM/ACE File.
   •  To generate JTAG (SVF/XSVF/STPL) files (FPGAs and CPLDs), double-click Manage Configuration Project (iMPACT). For more information, see Generating an SVF, XSVF, or STAPL File.
     The first time you configure your device, the tools walk you through the process of setting up your configuration project options. On subsequent runs, the tools use the settings stored in your iMPACT Project File (IPF). To edit the IPF file, use the Manage Configuration Project (iMPACT) process.

PROM Files

Xilinx FPGAs are CMOS configurable latch (CCL)-based and must be configured every time power is cycled from a non-volatile source. The most common method of programming Xilinx FPGAs is by using Xilinx PROMs connected to a chain of FPGAs. PROM files include information on the FPGA chain length and contain bitstreams that are reformatted for use with PROM programmers. Several PROM file formats are available: MCS, EXO, TEK, HEX, UFP, BIN, and ISC. iMPACT can directly program Xilinx PROM devices using MCS, EXO, and ISC file formats. In addition, some Xilinx FPGA families can be configured using supported SPI or BPI Flash devices. You must program these memory devices using PROM files created from the bitstreams of the targeted FPGAs.

When you create a PROM file using iMPACT, you must select one of the following types of PROM files to target:

•  Xilinx Flash/PROM
  iMPACT generates a PROM file you can use to program a Xilinx Flash/PROM (18V00, XCFxxS, XCFxxP, or XCF128X). iMPACT can directly program Xilinx Flash/PROM devices using MCS, EXO, and ISC file formats. If you are using a third party programmer, check the documentation that came with the software to see if a particular format is required.
•  Non-Volatile FPGA
  Spartan®-3AN devices are non-volatile FPGAs, which have internal Flash that is programmed using MCS, EXO, or ISC formatted files.
•  Serial Peripheral Interface (SPI) Flash
  SPI is a serial interface standard most commonly used in microprocessor and memory applications. SPI Flash uses this interface to provide direct access to memory addresses, only requiring a 4-pin interface to configure the FPGA. Certain Xilinx FPGAs support direct configuration using an SPI Flash. These FPGAs can be configured from the SPI Flash using a single image or a multiple-imaged PROM file. The multiple-imaged PROM file enables FPGA multi-boot applications. To program third party SPI Flash devices, iMPACT generates a PROM file.
•  Byte Peripheral Interface (BPI) Flash
  BPI is the Xilinx version of the standard parallel NOR flash interface (x8 and x16). Certain Xilinx FPGAs support direct configuration using a BPI Flash. These FPGAs can be configured from the BPI Flash using a single image or a multiple-imaged PROM file. The multiple-imaged PROM file enables FPGA multi-boot applications. For applications requiring larger data bus widths, you can use the Configure from Paralleled PROMs utility in iMPACT, which allows you to combine two x16 Xilinx PROMs together to create a x32 file format.
•  Generic Parallel PROM
  iMPACT generates a PROM file that you can use to program parallel PROMs made by third party companies. These PROMs are typically byte-wide, directly-accessible memory devices that require addresses for certain pins so that specific locations can be read. iMPACT allows you to generate PROM files for parallel PROMs; it does not support programming of parallel PROMs.

Note For information on which FPGAs support direct configuration by SPI and BPI Flash, see the Data Sheets or Device User Guides the for the device you are targeting.

System ACE CompactFlash (CF) Files

Xilinx System Advanced Configuration Environment (ACE) files are used with the System ACE device family, which features greater capacity and flexibility than Xilinx PROMs. The System ACE CompactFlash (CF) solution allows you to program an FPGA target chain or chains. This configuration solution is a chipset, which comprises an ACE controller device and a CompactFlash storage device.

Note For more information on using iMPACT to generate these files, see System ACE CF Settings. For more information on the System ACE CompactFlash solution, see the System ACE CF Solution Data Sheet.

Boundary Scan or JTAG Vector Files

Boundary scan files, also known as JTAG files, are script files that describe a sequence of boundary scan commands and data. To create these script files, iMPACT records the sequence of boundary scan actions in iMPACT and writes these sequences to the script file. Following are the different file formats and their uses:

•  SVF and STAPL files
  You can use serial vector format (SVF) files and STAPL files with automated test equipment (ATE) to test boards and to program Xilinx devices before sending the boards to your customers.
•  XSVF files
  You can use the Xilinx serial vector format (XSVF) file for embedded systems in which the FPGA is configured by an on-board microprocessor.

Note For information on boundary scan file generation, see Boundary-Scan Files.

Additional Resources

Additional information is available in the following Xilinx documentation.

Documentation	Topics Covered
Device User Guides	Device-specific configuration information
Data Sheets	Device specifications, including I/O standards
Common Issues and Debug Solutions	Troubleshooting information for configuration and programming
iMPACT Help Note In the Help Viewer, click the Synchronize TOC button to view all related Help topics.	iMPACT software